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100 Base-X Interface Module
ELECTRONICS INC.
EPF8046G
* Optimized to work with ML6692/94 PHY chip * * Guaranteed to operate with 8 mA DC bias at 70C on cable side * * Complies with or exceeds IEEE 802.3, 100 BX Standards * * Robust construction allows for most severe soldering processes *
Electrical Parameters @ 25 C
OCL @ 70C 100 KHz, 0.1 Vrms 8 mA DC Bias Cable Side 350H * Xmit -1 Insertion Loss (dB Max.) 1-100 MHz Rcv -1 1-20 MHz Xmit Rcv -18 -25 Return Loss (dB Min.) 60 MHz 80 MHz Common Mode Rejection (dB Min.) 30-100 MHz 200 MHz 500 MHz Crosstalk (dB Min.) [Between Channels] 10-100 MHz
Xmit Rcv Xmit -8 -20 -6
Rcv Xmit -20 -30
Rcv Xmit -30 -25
Rcv Xmit Rcv -25 * -20 -15 * -40
Isolation : 1500 Vrms * Cable Impedance : 100 * Rise Time : 3.0 nS Max.
*Optional
Schematic
Transmit Channel 1 8 16 Receive Channel 9
2 3 2CT:1CT
7 6 5
*
15 14
1CT:1CT
10 11 12
Package
A J
Pin 1 I.D. PCA EPF8046G Date Code Dim. Min. .970 .380 .223 .700 .003 .100 .500 .016 .008 .090 0 .025
Dimensions
(Inches) Max. Nom. .990 .400 .243 Typ. .020 Typ. .520 .022 .012 Typ. 8 .045 .030 .100 .092 .560 (Millimeters) Min. Max. Nom. 24.64 9.65 5.66 17.78 0.076 2.54 12.7 .406 .203 2.28 0 .635 25.15 10.16 6.17 Typ. .508 Typ. 13.20 .559 .305 Typ. 8 1.14 .762 2.54 2.34 14.22
N
Pad Layout
B
Q
P
D E
M
C
K L I
A B C D E F G H I J K L M N P Q
H
F
G
PCA ELECTRONICS, INC. 16799 SCHOENBORN ST. NORTH HILLS, CA 91343
CSF8046Ga
Rev. 4
12/16/96
Product performance is limited to specified parameters. Data is subject to change without prior notice.
TEL: (818) 892-0761 FAX: (818) 894-5791 http://www.pca.com
100 Base-X Interface Module
ELECTRONICS INC.
EPF8046G
The circuit below is a guideline for interconnecting PCA's EPF8046G with ML6692 or ML6694 chip applications. Further details can be obtained from the chip manufacturer application notes. Typical insertion loss of the isolation transformer is 0.5dB. This parameter covers the entire spectrum of the encoded signals in 100 BX protocol. Under terminated conditions, to transmit a 2V pk-pk signal across the cable, you must adjust the chips supporting resistor to get at least 2.12V pk-pk across the transmit pins. Note that in the 100 BX application, you do not need a split primary. The reason is that there is no 10 Base-T to negotiate. The receiver side can be terminated as shown or a by single 100 with primary center tap taken to ground via a suitable cap. The phantom resistors shown around the connector have been known to suppress unwanted radiation that unused wires pick up from the immediate environment. Their placement and use are to be considered carefully before a design is finalized. Also, in, some cases , there has been EMI improvement by taking pin 12 to Chassis via a cap. It may not be required: this can be decided only during an EMC test. Same comments apply to pin 5 connection. It is recommended that there be a neat separation of ground planes in the layout. It is generally accepted practice to limit the plane off at least 0.05 inches away from the chip side pins of EPF8046G. There need not be any ground plane beyond this plane. For best results, PCB designer should design the outgoing traces preferably to be 50 , balanced and well coupled to achieve minimum radiation from these traces.
Typical Application Circuit for UTP
+5V
3
200 200
8 7 9
1 Xmit 2 3 Rcv 6
TX+
1 2 14
10
50
ML6692 or ML6694
TX-
RJ45*
4 5
RX+ RX50 50
16 15 .1 F
EPF8046G
5 12
50
7 8
Capacitor
Chassis Ground
Notes : * NIC Side is shown. Hub side connection will swap pins 3-6 with 1-2.
PCA ELECTRONICS, INC. 16799 SCHOENBORN ST. NORTH HILLS, CA 91343
CSF8046Gb
Rev. 3
12/13/96
TEL: (818) 892-0761 FAX: (818) 894-5791 http://www.pca.com

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